State Machine Design Using Cmod S6 Digital Electronics 2014 Project Lead The Way, Inc. State Machine Design This presentation will Define a state machine and Illustrate the block diagram for a state machine. Provide several examples of everyday items that are controlled by state machines. Describe the steps in the state machine design process. Provide an example of a state machine design. 2 State Machine A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal flip-flops progress through a predictable sequence of states in response to a clock and other input signals. Input(s)
Input Combo Logic Clock Memory Flip-Flops Output Combo Logic Output(s) 3 Parts of a State Machine Input Combinational Logic Memory Output Combinational Logic Input(s) Input
Combo Logic Clock Memory Flip-Flops Output Combo Logic Output(s) 4 Input Combinational Logic What should happen next based on the buttons, switches, and other inputs? Input(s) Input Combo Logic
Clock Memory Flip-Flops Output Combo Logic Output(s) 5 Memory Flip-Flops determine the number of states in the design and trigger the state transitions based on the inputs. Input(s) Input Combo Logic Clock
Memory Flip-Flops Output Combo Logic Output(s) 6 Output Combinational Logic What should motors, indicators, and other outputs do once the flip-flops have caused the transition to a new state? Input(s) Input Combo Logic Clock Memory Flip-Flops
Output Combo Logic Output(s) 7 Examples of State Machines Many everyday devices are controlled by state machines. Traffic Lights Garage Door Numeric Keypads Vending Machines 8 State Machine Design 1. Create a State Graph a. Determine the number of States and label b. Determine the number of State Variables and label (How many flip-flops needed?) c. Label Outputs and Encode Outputs to States 2. Create State Transition Table from the State Graph 3. Write and Simplify Design Equations from the State Transition Table
4. Design Circuit 9 State Graphs A state graph shows the sequence of states that the state machine will transition to on each clock transition. This is an example of a state graph with four states (S0-S3). 10 State Graphs Each state bubble is labeled (S0,S1,S2,S3). These labels are arbitrary. Each transition arc is labeled with the values of the input variables that make the transition occur. 11
Anatomy of a State Graph Transition Arc (For Input X=0) Hold State State Bubble Input Variable (X) X=0 S0 Qa Qb 0 0 Y=0 & Z=1 State Variables (Qa & Qb) Output Variables (Y & Z) State (S0) X=1 Transition Arc (For Input X=1) Next State
Next State Bubble 12 State Variables The state variables are actually the outputs of the memory flip-flops. For that reason they are typically labeled Qa, Qb, etc. S0 Qa Qb 0 0 This four state example would require (2) flip-flop (Qa and Qb) to clock through four states (S0-S3). 1st State (SO) Qa Qb = 0 0 2nd State (S1) Qa Qb = 0 1 3rd State (S2) Qa Qb = 1 0 4th State (S3) Qa Qb = 1 1 13
State Variables If a 5th state was needed: Can you guess how many flip-flops and state variables you would need? (It is not possible to have exactly 5 states) How many states would go un-used? 1st State (SO) Qa Qb = 0 0 2nd State (S1) Qa Qb = 0 1 3rd State (S2) Qa Qb = 1 0 4th State (S3) Qa Qb = 1 1 5th State (S4) ??????? = ????? 14 Output Variables Each state bubble is assigned output variables. This example has 4 output variables based on what state it is in. 15
State Graphs to State Transition Tables 16 State Transition Tables State Transition Tables are then created from the State Graph. They describe the Present State (inputs) and the Next State (outputs) associated with each state (S0-S3). 17 State Transition Tables Notice that each state occupies 2 lines on the State Transition Table. That is because (in this example) each transition is triggered by only one of 4 possible inputs at any time. For: Input that causes transition: S0 OS = 0 ;OS = 1
S1 OL = 0 ;OS = 1 S2 CS = 0 ;CS =1 S3 CL = 0 ;CL = 1 18 State Transition Tables In a state machine, the Next State is actually the output from the Memory flip-flops (Qa* Qb*) when an input is changed. Qa* = Da for the next state on one flip-flop and Qb* = Db for the next state on the other flip-flop 19 State Transition Tables The outputs from the Memory flip-flops are linked to the Input Combinational Logic. That way a transition is made on the next clock signal to the next state. Qa* = Da for the next state on one flip-flop and
Qb* = Db for the next state on the other flip-flop Input(s) Input Combo Logic Clock Memory Flip-Flops Output Combo Logic Output(s) 20 Design Equations From the State Transition Table you can now determine the unsimplified expressions for the: Input Combinational Logic
Da=Qa* Db=Qb* Output Combinational Logic This example has (4) outputs MO Motor Open Signal MC Motor Close Signal GO Gate Open Indicator GC Gate Closed Indicator 21 State Machine Design Example Design a state machine that will count out the last four digits of a phone number ONLY when an Enable pushbutton is pressed. The output should hold the last number until the Enable button is pressed again. (Example 585-476-4691) 4 6 9 1 Whenever the Enable is a logic (1), the outputs will continuously cycle through the four values 4,6,9,1. Whenever the Enable is a logic (0), the outputs will hold at their current values. For this design any form of combinational logic may be used, but the sequential logic must be limited to D flip-flops. Enable Clock Phone
Numbers C3 C2 C1 C0 22 Step 1: Create State Graph (# of States?) EN = 0 EN = 1 S0 EN = 1 4 EN = 0 S3 S1
1 6 EN = 0 S2 EN = 1 EN = 1 9 EN = 0 23 Step 2: Determine # of State Variables and Assign EN = 0 EN = 1 S0 EN = 1 Qa Qb
0 0 4 EN = 0 S3 S1 Qa Qb 1 1 Qa Qb 0 1 1 6 EN = 0 S2 EN = 1 Qa Qb 1 0
EN = 1 9 EN = 0 24 Step 3: Encode Outputs to States (# Displayed?) EN = 0 EN = 1 S0 EN = 1 Qa Qb 0 0 4 EN = 0 S3
Qa Qb 1 0 EN = 1 9 EN = 0 25 Step 4: Create State Transition Table Inputs Input State State Present State Outputs Next State
Qa Qb EN S0 0 0 0 S0 0 S0 0 0 1
S1 S1 0 1 0 S1 0 1 S2 1 S2 F/F Inputs Qa* Qb*
Encoded Outputs Da Db C3 C2 C1 C0 0 0 0 0 1
0 0 0 1 0 1 0 1 0 0 S1 0 1
0 1 0 1 1 0 1 S2 1 0 1 0 0
1 1 0 0 0 S2 1 0 1 0 1 0 0
1 1 0 1 S3 1 1 1 1 1 0 0 1
S3 1 1 0 S3 1 1 1 1 0 0 0 1
S3 1 1 1 S0 0 0 0 0 0 0 0 1
See Slide Notes for a detailed description 26 Step 5: Write and Simplify Design Equations Da Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Da Qa Qb EN Qa EN Qa Qb Db Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Db Qb EN Qb EN Db Qb EN C3 Qa Qb EN Qa Qb EN Qa Qb C2 Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Qa C1 Qa Qb EN Qa Qb EN Qa Qb C0 Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Qa 27 Step 6: Circuit Design AOI Simplified Can you think of a better way to impliment the logic for Db ? 28 Step 7:
Circuit Design Simplified Further? Da Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Da Qa Qb EN Qa EN Qa Qb Db Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Db Qb EN Qb EN Db Qb EN C3 Qa Qb EN Qa Qb EN Qa Qb C2 Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Qa C1 Qa Qb EN Qa Qb EN Qa Qb C0 Qa Qb EN Qa Qb EN Qa Qb EN Qa Qb EN Qa 29 Step 8: Circuit Design Simplified Further XOR 30 State Machine Block Diagram / Schematic 31
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