Lecture 1: Course Introduction and Overview

Lecture 1: Course Introduction and Overview

CS252 Graduate Computer Architecture Lecture 15: Instruction Level Parallelism and Dynamic Execution March 11, 2002 Prof. David E. Culler Computer Science 252 Spring 2002 3/12/02 CS252/Culler Lec 15.1 Recall from Pipelining Review Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Ideal pipeline CPI: measure of the maximum performance attainable by the implementation Structural hazards: HW cannot support this combination of instructions Data hazards: Instruction depends on result of prior instruction still in the pipeline Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps) 3/12/02 CS252/Culler Lec 15.2 Recall Data Hazard Resolution: In-order issue, in-order completion and r6,r2,r7 or r8,r2,r9 3/12/02 Reg DMem Ifetch Reg Bubble Ifetch Bubble Reg Bubble Ifetch Reg Reg DMem DMem Reg Extend to Multiple instruction issue? What if load had longer delay? Can and issue? ALU sub r4,r1,r6 Ifetch ALU O r

d e r lw r1, 0(r2) ALU I n s t r. ALU Time (clock cycles) Reg DMem CS252/Culler Lec 15.3 Reg ALU Ifetch Reg Add In-Order Issue, Out-of-order Completion DMem DMem Reg Which hazards are present? RAW? WAR? WAW? loadr3 <- r1, r2 add r1 <- r5, r2 sub r3 <- r3, r1 or r3 <- r2, r1 Register Reservations when issue mark destination register busy till complete check all register reservations before issue 3/12/02 CS252/Culler Lec 15.4 Ideas to Reduce Stalls Chapter 3 Chapter 4 3/12/02 Technique Dynamic scheduling Dynamic branch prediction Iss uing multiple instructions per cycle Speculation Dynamic memory disambiguation Loop unrolling Basic compiler pipeline scheduling Compiler dependence analysis Sof tware pipelining and trace scheduling

Compiler speculation Reduces Data hazard stalls Control stalls I deal CPI Data and control stalls Data hazard stalls involving memory Control hazard stalls Data hazard stalls I deal CPI and data hazard stalls I deal CPI and data hazard stalls I deal CPI, data and control stalls CS252/Culler Lec 15.5 Instruction-Level Parallelism (ILP) Basic Block (BB) ILP is quite small BB: a straight-line code sequence with no branches in except to the entry and no branches out except at the exit average dynamic branch frequency 15% to 25% => 4 to 7 instructions execute between a pair of branches Plus instructions in BB likely to depend on each other To obtain substantial performance enhancements, we must exploit ILP across multiple basic blocks Simplest: loop-level parallelism to exploit parallelism among iterations of a loop Vector is one way If not vector, then either dynamic via branch prediction or static via loop unrolling by compiler 3/12/02 CS252/Culler Lec 15.6 Data Dependence and Hazards InstrJ is data dependent on InstrI InstrJ tries to read operand before InstrI writes it I: add r1,r2,r3 J: sub r4,r1,r3 or InstrJ is data dependent on InstrK which is dependent on InstrI Caused by a True Dependence (compiler term) If true dependence caused a hazard in the pipeline, called a Read After Write (RAW) hazard 3/12/02 CS252/Culler Lec 15.7 Data Dependence and Hazards Dependences are a property of programs Presence of dependence indicates potential for a hazard, but actual hazard and length of any stall is a property of the pipeline Importance of the data dependencies 1) indicates the possibility of a hazard 2) determines order in which results must be calculated 3) sets an upper bound on how much parallelism can possibly be exploited Today looking at HW schemes to avoid hazard 3/12/02 CS252/Culler Lec 15.8 Name Dependence #1: Anti-dependence Name dependence: when 2 instructions use same register or memory location, called a name, but no flow of data between the instructions associated with that name; 2 versions of name dependence InstrJ writes operand before InstrI reads it I: sub r4,r1,r3

J: add r1,r2,r3 K: mul r6,r1,r7 Called an anti-dependence in compiler work. This results from reuse of the name r1 If anti-dependence caused a hazard in the pipeline, called a Write After Read (WAR) hazard 3/12/02 CS252/Culler Lec 15.9 Name Dependence #2: Output dependence InstrJ writes operand before InstrI writes it. I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Called an output dependence by compiler writers This also results from the reuse of name r1 If anti-dependence caused a hazard in the pipeline, called a Write After Write (WAW) hazard 3/12/02 CS252/Culler Lec 15.10 ILP and Data Hazards program order: order instructions would execute in if executed sequentially 1 at a time as determined by original source program HW/SW goal: exploit parallelism by preserving appearance of program order modify order in manner than cannot be observed by program must not affect the outcome of the program Ex: Instructions involved in a name dependence can execute simultaneously if name used in instructions is changed so instructions do not conflict 3/12/02 Register renaming resolves name dependence for regs Either by compiler or by HW add r1, r2, r3 sub r2, r4,r5 and r3, r2, 1 CS252/Culler Lec 15.11 Control Dependencies Every instruction is control dependent on some set of branches, and, in general, these control dependencies must be preserved to preserve program order if p1 { S1; }; if p2 { S2; } S1 is control dependent on p1, and S2 is control dependent on p2 but not on p1. 3/12/02 CS252/Culler Lec 15.12 Control Dependence Ignored Control dependence need not always be preserved willing to execute instructions that should not have been executed, thereby violating the control dependences, if can do so without affecting correctness of the program Instead, 2 properties critical to program

correctness are exception behavior and data flow 3/12/02 CS252/Culler Lec 15.13 Exception Behavior Preserving exception behavior => any changes in instruction execution order must not change how exceptions are raised in program (=> no new exceptions) Example: DADDU R2,R3,R4 BEQZ R2,L1 LW R1,0(R2) L1: Problem with moving LW before BEQZ? 3/12/02 CS252/Culler Lec 15.14 Data Flow Data flow: actual flow of data values among instructions that produce results and those that consume them branches make flow dynamic, determine which instruction is supplier of data Example: DADDU R1,R2,R3 BEQZ R4,L DSUBU R1,R5,R6 L: OR R7,R1,R8 OR depends on DADDU or DSUBU? Must preserve data flow on execution 3/12/02 CS252/Culler Lec 15.15 CS 252 Administrivia Final Project Proposals due 3/17 send URL to page containing title & participants problem statement annotated bibliography well monitor progress through the pages Assignment 3 out, due in 3/19 Quiz 3/21 3/12/02 CS252/Culler Lec 15.16 Advantages of Dynamic Scheduling Handles cases when dependences unknown at compile time (e.g., because they may involve a memory reference) It simplifies the compiler Allows code that compiled for one pipeline to run efficiently on a different pipeline Hardware speculation, a technique with significant performance advantages, that builds on dynamic scheduling 3/12/02 CS252/Culler Lec 15.17

HW Schemes: Instruction Parallelism Key idea: Allow instructions behind stall to proceed DIVD ADDD SUBD F0,F2,F4 F10,F0,F8 F12,F8,F14 Enables out-of-order execution and allows out-of-order completion Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution In a dynamically scheduled pipeline, all instructions pass through issue stage in order (in-order issue) 3/12/02 CS252/Culler Lec 15.18 Dynamic Scheduling Step 1 Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue Split the ID pipe stage of simple 5stage pipeline into 2 stages: IssueDecode instructions, check for structural hazards Read operandsWait until no data hazards, then read operands 3/12/02 CS252/Culler Lec 15.19 A Dynamic Algorithm: Tomasulos Algorithm For IBM 360/91 (before caches!) Goal: High Performance without special compilers Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations This led Tomasulo to try to figure out how to get more effective registers renaming in hardware! Why Study 1966 Computer? The descendants of this have flourished! Alpha 21264, HP 8000, MIPS 10000, Pentium III, PowerPC 604, 3/12/02 CS252/Culler Lec 15.20 Tomasulo Algorithm Control & buffers distributed with Function Units (FU) FU buffers called reservation stations; have pending operands Registers in instructions replaced by values or pointers to reservation stations(RS); form of register renaming ; avoids WAR, WAW hazards More reservation stations than registers, so can do optimizations compilers cant Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs Load and Stores treated as FUs with RSs as well Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue 3/12/02 CS252/Culler Lec 15.21 Tomasulo Organization

FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations FP FP FPadders adders FPmultipliers multipliers Common Data Bus (CDB) 3/12/02 To Mem CS252/Culler Lec 15.22 Reservation Station Components Op:Operation to perform in the unit (e.g., + or ) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result statusIndicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. 3/12/02 CS252/Culler Lec 15.23 Three Stages of Tomasulo Algorithm 1. Issueget instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Executeoperate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write resultfinish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (go to bus) Common data bus: data + source (come from bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast Example speed: 3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for / 3/12/02 CS252/Culler Lec 15.24

Instruction stream Tomasulo Example Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result Load1 Load2 Load3 Register result status: Clock 0 No No No 3 Load/Buffers Reservation Stations: Time Name Busy Add1 No Add2 No FU count Add3 No down Mult1 No Mult2 No Busy Address Op S1 Vj S2 Vk RS Qj RS Qk 3 FP Adder R.S. 2 FP Mult R.S. F0 F2 F4

F6 F8 F10 F12 ... F30 FU Clock cycle counter 3/12/02 CS252/Culler Lec 15.25 Tomasulo Example Cycle 1 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Register result status: Clock 1 3/12/02 FU Busy Address Load1 Load2 Load3 Op S1 Vj S2

Vk RS Qj RS Qk F0 F2 F4 F6 F8 Yes No No 34+R2 F10 F12 ... F30 Load1 CS252/Culler Lec 15.26 Tomasulo Example Cycle 2 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Register result status: Clock 2

FU Busy Address Load1 Load2 Load3 Op S1 Vj S2 Vk RS Qj RS Qk F0 F2 F4 F6 F8 Load2 Yes Yes No 34+R2 45+R3 F10 F12 ... F30 Load1 Note: Can have multiple loads outstanding 3/12/02 CS252/Culler Lec 15.27 Tomasulo Example Cycle 3 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2

Exec Write Issue Comp Result 1 2 3 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes MULTD Mult2 No Register result status: Clock 3 FU F0 Busy Address 3 S1 Vj Load1 Load2 Load3 S2 Vk RS Qj Yes Yes No 34+R2 45+R3 F10 F12 RS Qk R(F4) Load2 F2 Mult1 Load2 F4 F6 F8 ... F30 Load1 Note: registers names are removed (renamed) in Reservation Stations; MULT issued CS252/Culler 3/12/02 Lec 15.28 Tomasulo Example Cycle 4 Instruction status: Instruction LD F6

LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 Reservation Stations: Busy Address 3 4 4 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 No Yes No 45+R3 F10 F12 Time Name Busy Op Add1 Yes SUBD M(A1) Load2 Add2 No Add3 No Mult1 Yes MULTD R(F4) Load2 Mult2 No

Register result status: Clock 4 FU F0 Mult1 Load2 ... F30 M(A1) Add1 Load2 completing; what is waiting for Load2? 3/12/02 CS252/Culler Lec 15.29 Tomasulo Example Cycle 5 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk

F2 F4 F6 F8 Time Name Busy Op 2 Add1 Yes SUBD M(A1) M(A2) Add2 No Add3 No 10 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 5 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 M(A1) Add1 Mult2 Timer starts down for Add1, Mult1 3/12/02 CS252/Culler Lec 15.30 Tomasulo Example Cycle 6 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6

Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op 1 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add1 Add3 No 9 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 6 FU F0 Mult1 M(A2) Add2 No No No F10 F12 ... F30 Add1 Mult2 Issue ADDD here despite name dependency on F6? CS252/Culler 3/12/02 Lec 15.31 Tomasulo Example Cycle 7 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8

DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 Busy Address 4 5 Load1 Load2 Load3 7 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op 0 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add1 Add3 No 8 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 7 FU F0 No No No

Mult1 M(A2) Add2 F10 F12 ... F30 Add1 Mult2 Add1 (SUBD) completing; what is waiting for it? CS252/Culler 3/12/02 Lec 15.32 Tomasulo Example Cycle 8 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 S1 Vj S2 Vk RS Qj

RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No 2 Add2 Yes ADDD (M-M) M(A2) Add3 No 7 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 8 3/12/02 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 Add2 (M-M) Mult2 CS252/Culler Lec 15.33 Tomasulo Example Cycle 9 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3

4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No 1 Add2 Yes ADDD (M-M) M(A2) Add3 No 6 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 9 3/12/02 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 Add2 (M-M) Mult2 CS252/Culler Lec 15.34 Tomasulo Example Cycle 10 Instruction status: Instruction LD F6 LD

F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 4 5 7 8 Busy Address Load1 Load2 Load3 10 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No 0 Add2 Yes ADDD (M-M) M(A2) Add3 No 5 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 10

FU F0 No No No Mult1 M(A2) F10 F12 ... F30 Add2 (M-M) Mult2 Add2 (ADDD) completing; what is waiting for it? CS252/Culler 3/12/02 Lec 15.35 Tomasulo Example Cycle 11 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11

S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 4 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 11 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 Write result of ADDD here? All quick instructions complete in this cycle! CS252/Culler 3/12/02 Lec 15.36 Tomasulo Example Cycle 12 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8

k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 3 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 12 3/12/02 FU F0 Mult1 M(A2) No No No F10

F12 ... F30 (M-M+M)(M-M) Mult2 CS252/Culler Lec 15.37 Tomasulo Example Cycle 13 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2

F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 2 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 13 3/12/02 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 CS252/Culler Lec 15.38 Tomasulo Example Cycle 14 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6

Reservation Stations: Busy Address 3 4 4 5 Load1 Load2 Load3 7 8 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No 1 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 Register result status: Clock 14 3/12/02 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 CS252/Culler Lec 15.39 Tomasulo Example Cycle 15 Instruction status: Instruction LD F6

LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: Busy Address 3 4 15 7 4 5 Load1 Load2 Load3 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 8 Time Name Busy Op Add1 No Add2 No Add3 No 0 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1

Register result status: Clock 15 FU F0 Mult1 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 Mult1 (MULTD) completing; what is waiting for it? CS252/Culler 3/12/02 Lec 15.40 Tomasulo Example Cycle 16 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 4 5 16 8 Load1 Load2 Load3

10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 40 Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock 16 FU F0 Busy Address M*F4 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 Just waiting for Mult2 (DIVD) to complete 3/12/02 CS252/Culler Lec 15.41 Faster than light computation (skip a couple of cycles) 3/12/02 CS252/Culler Lec 15.42 Tomasulo Example Cycle 55 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD

F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 4 5 16 8 Load1 Load2 Load3 10 11 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 1 Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock 55 3/12/02 FU F0

Busy Address M*F4 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Mult2 CS252/Culler Lec 15.43 Tomasulo Example Cycle 56 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 56 10 4 5 16 8 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj

RS Qk 56 FU F0 F2 F4 F6 F8 M*F4 M(A2) No No No 11 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 0 Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock Busy Address F10 F12 ... F30 (M-M+M)(M-M) Mult2 Mult2 (DIVD) is completing; what is waiting for it? CS252/Culler 3/12/02 Lec 15.44 Tomasulo Example Cycle 57 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2

Exec Write Issue Comp Result 1 2 3 4 5 6 Reservation Stations: 3 4 15 7 56 10 4 5 16 8 57 11 Load1 Load2 Load3 S1 Vj S2 Vk RS Qj RS Qk F2 F4 F6 F8 Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No Mult2 Yes DIVD M*F4 M(A1) Register result status: Clock 56 FU F0 Busy Address M*F4 M(A2) No No No F10 F12 ... F30 (M-M+M)(M-M) Result Once again: In-order issue, out-of-order

execution and out-of-order completion. 3/12/02 CS252/Culler Lec 15.45 Tomasulo Drawbacks Complexity delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon! Many associative stores (CDB) at high speed Performance limited by Common Data Bus Each CDB must go to multiple functional units high capacitance, high wiring density Number of functional units that can complete per cycle limited to one! Multiple CDBs more FU logic for parallel assoc stores Non-precise interrupts! We will address this later 3/12/02 CS252/Culler Lec 15.46 Tomasulo Loop Example Loop: MULTD SD F4 SUBI BNEZ LD F4 0 R1 R1 F0 0 F0 F2 R1 R1 #8 Loop R1 This time assume Multiply takes 4 clocks Assume 1st load takes 8 clocks (L1 cache miss), 2nd load takes 1 clock (hit) To be clear, will show clocks for SUBI, BNEZ Reality: integer instructions ahead of Fl. Pt. Instructions Show 2 iterations 3/12/02 CS252/Culler Lec 15.47 Loop Example Instruction status: ITER Instruction 1 1 1 Iter- 2 ation 2 Count 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0

F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Op Vj Exec Write Issue CompResult Load1 Load2 Load3 Store1 Store2 Store3 S1 Vk S2 Qj RS Qk 0 F0 R1 80 Code: LD MULTD SD SUBI BNEZ Fu No No No No No No Added Store Buffers F0 F4 F4 R1 R1 0 F0

0 R1 Loop R1 F2 R1 #8 Instruction Loop Register result status Clock Busy Addr F2 F4 F6 F8 F10 F12 ... F30 Fu Value of Register used for address, iteration control 3/12/02 CS252/Culler Lec 15.48 Loop Example Cycle 1 Instruction status: ITER Instruction 1 LD F0 j k 0 R1 1 Vj S1 Vk Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Exec Write Issue CompResult Op S2 Qj RS Qk

Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No No No No No 80 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 1 3/12/02 R1 80 F0 F2 F4 F6 F8 F10 F12 Fu Load1 CS252/Culler Lec 15.49 Loop Example Cycle 2 Instruction status: ITER Instruction 1 1 LD MULTD F0 F4

j k 0 F0 R1 F2 1 2 Vj S1 Vk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No S2 Qj RS Qk R(F2) Load1 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No No No No No 80 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ...

F30 Register result status Clock 2 3/12/02 R1 80 F0 Fu Load1 F2 F4 F6 F8 F10 F12 Mult1 CS252/Culler Lec 15.50 Loop Example Cycle 3 Instruction status: ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 j k 0 F0 0 R1 F2 R1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No Vj Exec Write Issue CompResult 1 2 3 S1 Vk S2 Qj RS Qk

R(F2) Load1 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No No Yes No No 80 80 Mult1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 3 R1 80 F0 Fu Load1 F2 F4 F6 F8 F10 F12 Mult1 Implicit renaming sets up data flow graphCS252/Culler 3/12/02 Lec 15.51 Loop Example Cycle 4 Instruction status: ITER Instruction

1 1 1 LD MULTD SD F0 F4 F4 j k 0 F0 0 R1 F2 R1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No Vj Exec Write Issue CompResult 1 2 3 S1 Vk S2 Qj RS Qk R(F2) Load1 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No No Yes No No 80 80 Mult1 Code: LD MULTD SD SUBI BNEZ

F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 4 R1 80 F0 Fu Load1 F2 F4 F6 F8 F10 F12 Mult1 Dispatching SUBI Instruction (not in FP queue) CS252/Culler 3/12/02 Lec 15.52 Loop Example Cycle 5 Instruction status: ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 j k 0 F0 0 R1 F2 R1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3

No Mult1 Yes Multd Mult2 No Vj Exec Write Issue CompResult 1 2 3 S1 Vk S2 Qj RS Qk R(F2) Load1 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No No Yes No No 80 80 Mult1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 5 R1 72 F0 Fu Load1 F2

F4 F6 F8 F10 F12 Mult1 And, BNEZ instruction (not in FP queue) 3/12/02 CS252/Culler Lec 15.53 Loop Example Cycle 6 Instruction status: ITER Instruction 1 1 1 2 LD MULTD SD LD F0 F4 F4 F0 j k 0 F0 0 0 R1 F2 R1 R1 1 2 3 6 Vj S1 Vk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No S2 Qj RS Qk R(F2) Load1 Busy Addr Fu

Load1 Load2 Load3 Store1 Store2 Store3 Yes Yes No Yes No No 80 72 80 Mult1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 6 R1 72 F0 Fu Load2 F2 F4 F6 F8 F10 F12 Mult1 Notice that F0 never sees Load from location 80 3/12/02 CS252/Culler Lec 15.54 Loop Example Cycle 7 Instruction status: ITER Instruction 1 1 1 2 2 LD

MULTD SD LD MULTD F0 F4 F4 F0 F4 j k 0 F0 0 0 F0 R1 F2 R1 R1 F2 1 2 3 6 7 Vj S1 Vk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd S2 Qj RS Qk R(F2) Load1 R(F2) Load2 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes Yes No Yes No No 80 72 80 Mult1

Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 7 R1 72 F0 Fu Load2 F2 F4 F6 F8 F10 F12 Mult2 Register file completely detached from computation First and Second iteration completely overlapped 3/12/02 CS252/Culler Lec 15.55 Loop Example Cycle 8 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0

F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 Vj S1 Vk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd S2 Qj RS Qk R(F2) Load1 R(F2) Load2 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes Yes No Yes Yes No 80 72 80 72 Mult1 Mult2 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1

R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 8 3/12/02 R1 72 F0 Fu Load2 F2 F4 F6 F8 F10 F12 Mult2 CS252/Culler Lec 15.56 Loop Example Cycle 9 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1

1 2 3 6 7 8 9 Vj S1 Vk S2 Qj Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd RS Qk R(F2) Load1 R(F2) Load2 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes Yes No Yes Yes No 80 72 80 72 Mult1 Mult2 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1

#8 ... F30 Register result status Clock 9 R1 72 F0 Fu Load2 F2 F4 F8 F10 F12 Mult2 Load1 completing: who is waiting? Note: Dispatching SUBI 3/12/02 F6 CS252/Culler Lec 15.57 Loop Example Cycle 10 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 4 Exec Write Issue CompResult 1 2

3 6 7 8 S1 Vk 9 10 10 S2 Qj Name Busy Op Vj Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd R(F2) Load2 RS Qk Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No Yes No Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 Fu 72 80 72 Mult1 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 10

R1 64 F0 Fu Load2 F2 F4 F8 F10 F12 Mult2 Load2 completing: who is waiting? Note: Dispatching BNEZ 3/12/02 F6 CS252/Culler Lec 15.58 Loop Example Cycle 11 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 3 4 Exec Write Issue CompResult 1 2 3 6 7 8 S1 Vk Name Busy Op Vj

Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) 9 10 10 11 S2 Qj RS Qk Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu Mult1 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 11 R1 64 F0 Fu Load3 F2

F4 F6 F8 F10 F12 Mult2 Next load in sequence 3/12/02 CS252/Culler Lec 15.59 Loop Example Cycle 12 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 2 3 Exec Write Issue CompResult 1 2 3 6 7 8 S1 Vk Name Busy Op Vj Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2)

9 10 10 11 S2 Qj RS Qk Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu Mult1 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 12 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12

Mult2 Why not issue third multiply? 3/12/02 CS252/Culler Lec 15.60 Loop Example Cycle 13 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 1 2 Exec Write Issue CompResult 1 2 3 6 7 8 S1 Vk Name Busy Op Vj Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) 9 10 10 11 S2

Qj RS Qk Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu Mult1 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 13 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult2 Why not issue third store? 3/12/02 CS252/Culler Lec 15.61 Loop Example Cycle 14

Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 0 1 Exec Write Issue CompResult 1 2 3 6 7 8 9 14 10 11 S1 Vk S2 Qj RS Qk Name Busy Op Vj Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) 10 Busy Addr Load1 Load2

Load3 Store1 Store2 Store3 No No Yes Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu Mult1 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 14 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult2 Mult1 completing. Who is waiting? 3/12/02 CS252/Culler Lec 15.62 Loop Example Cycle 15 Instruction status: ITER Instruction 1 1 1 2 2 2

LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 Reservation Stations: Time 0 Exec Write Issue CompResult 1 2 3 6 7 8 9 14 10 15 11 S1 Vk S2 Qj RS Qk Name Busy Op Vj Add1 No Add2 No Add3 No Mult1 No Mult2 Yes Multd M[72] R(F2) 10 15 Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No

Yes Yes Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu [80]*R2 Mult2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 15 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult2 Mult2 completing. Who is waiting? 3/12/02 CS252/Culler Lec 15.63 Loop Example Cycle 16 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD

F0 F4 F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 9 14 10 15 11 16 Vj S1 Vk S2 Qj RS Qk Reservation Stations: Time 4 Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No 10 15 R(F2) Load3 Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes

Yes No Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 64 80 72 Fu [80]*R2 [72]*R2 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 16 3/12/02 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult1 CS252/Culler Lec 15.64 Loop Example Cycle 17 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4

F4 F0 F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 9 14 10 15 11 16 Vj S1 Vk S2 Qj RS Qk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No 10 15 R(F2) Load3 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes Yes Yes

64 80 72 64 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 [80]*R2 [72]*R2 Mult1 Register result status Clock 17 3/12/02 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult1 CS252/Culler Lec 15.65 Loop Example Cycle 18 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0

F4 F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 9 14 18 10 15 10 15 Vj S1 Vk S2 Qj RS Qk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No 11 16 R(F2) Load3 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 No No Yes Yes Yes Yes

64 80 72 64 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 [80]*R2 [72]*R2 Mult1 Register result status Clock 18 3/12/02 R1 64 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult1 CS252/Culler Lec 15.66 Loop Example Cycle 19 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4

F4 j k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 9 14 18 10 15 19 10 15 19 11 16 Vj S1 Vk S2 Qj RS Qk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R(F2) Load3 Busy Addr Load1 Load2 Load3 Store1 Store2 Store3 No No Yes No Yes Yes Code: LD MULTD

SD SUBI BNEZ F0 F4 F4 R1 R1 Fu 64 72 64 [72]*R2 Mult1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 Register result status Clock 19 3/12/02 R1 56 F0 Fu Load3 F2 F4 F6 F8 F10 F12 Mult1 CS252/Culler Lec 15.67 Loop Example Cycle 20 Instruction status: ITER Instruction 1 1 1 2 2 2 LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 j

k 0 F0 0 0 F0 0 R1 F2 R1 R1 F2 R1 1 2 3 6 7 8 9 14 18 10 15 19 10 15 19 11 16 20 Vj S1 Vk S2 Qj RS Qk Reservation Stations: Time Exec Write Issue CompResult Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R(F2) Load3 Busy Addr Fu Load1 Load2 Load3 Store1 Store2 Store3 Yes No Yes No No Yes 56

64 Mult1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 ... F30 64 Register result status Clock 20 R1 56 F0 Fu Load1 F2 F4 F6 F8 F10 F12 Mult1 Once again: In-order issue, out-of-order execution and out-of-order completion. 3/12/02 CS252/Culler Lec 15.68 Why can Tomasulo overlap iterations of loops? Register renaming Multiple iterations use different physical destinations for registers (dynamic loop unrolling). Reservation stations Permit instruction issue to advance past integer control flow operations Also buffer old values of registers - totally avoiding the WAR stall that we saw in the scoreboard. Other perspective: Tomasulo building data flow dependency graph on the fly. 3/12/02 CS252/Culler Lec 15.69 Tomasulos scheme offers 2 major advantages (1)the distribution of the hazard detection

logic distributed reservation stations and the CDB If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB If a centralized register file were used, the units would have to read their results from the registers when register buses are available. (2) the elimination of stalls for WAW and WAR hazards 3/12/02 CS252/Culler Lec 15.70 What about Precise Interrupts? State of machine looks as if no instruction beyond faulting instructions has issued Tomasulo had: In-order issue, out-of-order execution, and out-of-order completion Need to fix the out-of-order completion aspect so that we can find precise breakpoint in instruction stream. 3/12/02 CS252/Culler Lec 15.71 Relationship between precise interrupts and specultation: Speculation: guess and check Important for branch prediction: Need to take our best shot at predicting branch direction. If we speculate and are wrong, need to back up and restart execution to point at which we predicted incorrectly: This is exactly same as precise exceptions! Technique for both precise interrupts/exceptions and speculation: inorder completion or commit 3/12/02 CS252/Culler Lec 15.72 HW support for precise interrupts Need HW buffer for results of uncommitted instructions: reorder buffer 3 fields: instr, destination, value Use reorder buffer number FP instead of reservation station Op when execution completes Queue Supplies operands between execution complete & commit (Reorder buffer can be operand source => more registers like RS) Res Stations Instructions commit FP Adder Once instruction commits, result is put into register As a result, easy to undo speculated instructions on mispredicted branches or exceptions 3/12/02

Reorder Buffer FP Regs Res Stations FP Adder CS252/Culler Lec 15.73 Four Steps of Speculative Tomasulo Algorithm 1.Issueget instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination (this stage sometimes called dispatch) 2.Executionoperate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result; when both in reservation station, execute; checks RAW (sometimes called issue) 3.Write resultfinish execution (WB) Write on Common Data Bus to all awaiting FUs & reorder buffer; mark reservation station available. 4.Commitupdate register with reorder result When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer. Mispredicted branch flushes reorder buffer (sometimes called graduation) 3/12/02 CS252/Culler Lec 15.74 Program Counter Valid Exceptions? Result Reorder Table FP Op Queue Res Stations FP Adder Compar network Dest Reg What are the hardware complexities with reorder buffer (ROB)? Reorder Buffer FP Regs Res Stations FP Adder How do you find the latest version of a register? (As specified by Smith paper) need associative comparison network Could use future file or just use the register result status buffer to track which specific reorder buffer has received the value Need as many ports on ROB as register file 3/12/02 CS252/Culler Lec 15.75 Summary Reservations stations: implicit register renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards of Scoreboard Allows loop unrolling in HW Not limited to basic blocks

(integer units gets ahead, beyond branches) Today, helps cache misses as well Dont stall for L1 Data cache miss (insufficient ILP for L2 miss?) Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264 3/12/02 CS252/Culler Lec 15.76

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