ECE 545—Introduction to VHDL Lecture 9

ECE 545—Introduction to VHDL Lecture 9

Lecture 17 PicoBlaze Overview ECE 448 FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview Recommended reading PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs (search for it using Google or Xilinx website documentation search) ECE 448 FPGA and ASIC Design with VHDL

2 Block diagram of a Single-Purpose Processor (FSMD Finite State Machine with Datapath) ECE 448 FPGA and ASIC Design with VHDL 3 Block diagram of a General-Purpose Processor (Microcontroller) ECE 448 FPGA and ASIC Design with VHDL 4

PicoBlaze ECE 448 FPGA and ASIC Design with VHDL 5 PicoBlaze Overview 8-bit Register File of PicoBlaze Address 0 7

1 7 7 7 2 3 4 5 6 7 F

7 7 7 s0 s1 s2 s3 s4 s5 s6 s7 7 7

0 0 0 0 0 0 0 0 sF 0 16 Registers

Definition of Flags Flags are set or reset after ALU operations Zero flag - Z Z=1 0 zero condition if result = 0 otherwise Carry flag - C overflow, underflow, or various conditions

Example* C=1 if result > 28-1 or result < 0 0 otherwise *Applies only to addition or subtraction related instructions, refer to following slides otherwise Interface of PicoBlaze

ECE 448 FPGA and ASIC Design with VHDL 9 Development Flow of a System with PicoBlaze ECE 448 FPGA and ASIC Design with VHDL 10 PicoBlaze Programming Model

ECE 448 FPGA and ASIC Design with VHDL 11 Syntax and Terminology Syntax Example Definition sX s15 Value at register 15

KK 14 Value 14 PORT(KK) PORT(2) PORT((sX)) PORT((s10)) RAM(KK)

RAM(4) Input value from port 2 Input value from port specified by register 10 Value from RAM location 4 Addressing modes Immediate mode ADDCY s2, 15 SUB s7, 7 s2 + 15 + C s2 s7 7

s7 Direct mode INPUT s10, 28 PORT(28) s10 ADD s10 + s15 s10 s10, s15 Indirect mode INPUT s9, s2

PORT((s2)) s9 STORE s3, s10 s3 RAM((s10)) PicoBlaze ALU Instruction Set Summary (1) PicoBlaze ALU Instruction Set Summary (2) PicoBlaze ALU Instruction Set Summary (3) Logic instructions 1.

AND AND sX, sY sX and sY => sX AND sX, KK sX and KK => sX 2. OR OR sX, sY sX or sY => sX OR sX, KK sX or KK => sX 3. XOR XOR sX, sY sX xor sY => sX XOR sX, KK sX xor KK => sX

CZ IMM, DIR 0 IMM, DIR 0 IMM, DIR 0 Arithmetic Instructions (1)

CZ Addition ADD sX, sY sX + sY => sX ADD sX, KK sX + KK => sX ADDCY sX, sY sX + sY + CARRY => sX ADDCY sX, KK sX + KK + CARRY => sX IMM, DIR Arithmetic Instructions (2) CZ

Subtraction SUB sX, sY sX sY => sX SUB sX, KK sX KK => sX SUBCY sX, sY sX sY CARRY => sX SUBCY sX, KK sX KK CARRY => sX IMM, DIR Test and Compare Instructions CZ TEST

IMM, DIR TEST sX, sY C = parity of sX and sY => none TEST sX, KK the result sX and KK => none COMPARE COMPARE sX, sY

sX sY => none COMPARE sX, KK sX KK => none IMM, DIR Data Movement Instructions (1) CZ LOAD IMM, DIR LOAD sX, sY sY => sX LOAD sX, KK KK => sX

-- Data Movement Instructions (2) CZ DIR, IND STORE -- STORE sX, KK sX => RAM(KK) STORE sX, (sY) sX => RAM((sY)) DIR, IND

FETCH FETCH sX, KK RAM(KK) => sX FETCH sX, (sY) RAM((sY)) => sX -- Data Movement Instructions (3) DIR, IND INPUT CZ

-- INPUT sX, KK sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) OUTPUT OUTPUT sX, KK PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= DIR, IND

-- Edit instructions - Shifts *All shift instructions affect Zero and Carry flags Edit instructions - Rotations *All rotate instructions affect Zero and Carry flags Program Flow Control Instructions (1) JUMP AAA

PC <= AAA JUMP C, AAA if C=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if C=0 then PC <= AAA else PC <= PC + 1 JUMP Z, AAA if Z=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if Z=0 then PC <= AAA else PC <= PC + 1 Program Flow Control Instructions (2) CALL AAA TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA

CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1 CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1 Program Flow Control Instructions (3) RETURN PC <= STACK[TOS] + 1; TOS <= TOS - 1 RETURN C | Z if C | Z =1 then

PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1 RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1 Interrupt Related Instructions RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE

PC <= STACK[TOS] ; TOS <= TOS 1; I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0;

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