Another Performance Evaluation of Memory Hierarchy in Embedded Systems Nelson Barnes CPE 631 04/14/03 Outline Introduction Related Work Problem Statement Proposed Solutions Experimental Setup Experimental Results Conclusions 02/27/20 UAH, ECE 2 Introduction Why is cache design so important in embedded systems? 02/27/20 UAH, ECE 3 Cache Design Parameters Cache organization
Unified vs. Split (Instruction + Data) caches Cache size Cache block (line) size Block placement policy Direct-mapped, associative Block fully-associative, set- replacement policy Random, Least-Recently Used (LRU), Round-robin, Pseudo-LRU, OPT (Optimal) 02/27/20 UAH, ECE 4 Related Work Mibench vs. NetBench 02/27/20 UAH, ECE
5 Problem Statement Comprehensive performance evaluation of cache design issues in embedded systems Performance metrics 02/27/20 Split versus unified cache Cache placement and size Cache block size Block replacement policy Static measure: the number of cache misses per 1K instructions executed measured at the end of application execution Dynamic measure: The number of cache misses per 1K instructions executed measured on every 100K instructions executed UAH, ECE 6 Proposed Solution Why use NetBench? 02/27/20
UAH, ECE 7 Experimental Setup ARM version of the SimpleScalar toolset Sim-cache Sim-cheetah NetBench Applications include: Micro-Level Programs IP-Level Programs Route IPv4 routing DRR Deficit round robin Application-Level Programs 02/27/20
CRC Checksum calculation TL Table lookup DH Public key encryption/decryption MD5 Message digest algorithm (secure signature) UAH, ECE 8 Experimental Setup Cache memory setup Split first level instruction and data Unified first level cache Cache parameters Cache size ranging from 0.5KB to 32KB Cache associativity direct mapped, 2-way, 4-way, and 8-way set associative Cache replacement policies FIFO, Random, LRU, pLRUt, pLRUm, and Optimal Cache block size 32B, 64B 02/27/20 UAH, ECE 9 Experimental Setup (contd) Instructions
ARM Core ARM Core 02/27/20 L1I $ Data L1D $ Instructions & Data L1U $ UAH, ECE 10 MiBench Experimental Results Data Cache Misses Data Cache Misses Misses per 1000 instructions 200 180 160 140 120 100 lame 80
1.6 108.1 75.2 50.2 28.8 12.5 4.0 1.2 17 Experimental Results NetBench Discussion 02/27/20 UAH, ECE 18 Conclusions Split caches outperform the equivalent unified cache for relatively small direct mapped caches Unified cache almost always outperforms the split caches for set-associative caches 02/27/20 UAH, ECE 19 Conclusions
Increasing cache associativity reduces the number of cache misses (up to 8-way associative caches) more beneficial for data and unified caches than for instruction caches Pseudo-LRU techniques perform as well as LRU for data caches Random performs the best for instruction caches Relatively significant difference between optimal replacement policy and the best nonoptimal policy 02/27/20 UAH, ECE 20
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