Transcription

Module5www.learnabout-electronics.orgDigital Electronics5.0 Sequential LogicWhat you’ll learn in Module 5Section 5.0 Introduction to SequentialLogic Circuits.Section 5.1 Clock Circuits. RC Clock Generators. Crystal Clock Generators.Section 5.2 SR Flip-flops. SR Flip-flops. RS Latches. Clocked SR FlipFlops.Section 5.3 D-Type Flip-flops. D Type Flip-flop operation. Edge triggered flip-flops. Toggle flip-flops. D Type master slave flip-flops. Data timing in flip-flops.Section 5.4 JK Flip-flops. JK master slave flip-flop operation. Edge triggered JK flip-flops. JK Type flip-flop ICs. JK Type Flip-flop timing diagrams.Section 5.5 CMOS Flip-flops.D Type & JK flip-flops using CMOStechnology.Section 5.6 Counters Asynchronous (Ripple) Counters. Synchronous Counters. Counter ICs.Section 5.7 Registers. Parallel and serial loading. Shift Registers. Register ICs.Section 5.8 Arithmetic & Logic Unit.IntroductionThelogiccircuitsdiscussed in DigitalElectronics Module 4had output states thatdependedontheparticular combinationof logic states at theinput connections to thecircuit. For this reasonthese circuits are calledcombinationallogiccircuits.Module 5 looks atdigital circuits that useSEQUENTIAL LOGIC.In these circuits the output depends, not only on thecombination of logic states at its inputs, but also on the logicstates that existed previously. In other words the outputdepends on a SEQUENCE of events occurring at the circuitinputs. Examples of such circuits include clocks, flip-flops,bi-stables, counters, memories, and registers. The actions ofthese circuits depend on a range of basic sub-circuits.Clock CircuitsModule 5.1 deals with clock oscillators,which are basically types of square wavegenerators or oscillators that produce acontinuous stream of square waves or acontinuous train of pulses (a "square"wave whose mark to space ratio is NOT1:1). These pulses are used to sequencethe actions of other devices in thesequential logic circuit so that all the actions taking place inthe circuit are properly synchronised. Connecting digital components together.Section 5.9 Sequential Logic Quiz. Test your knowledge of Sequential Logic.DIGITAL ELECTRONICS 05.PDF1 E. COATES 2007 -2014

www.learnabout-electronics.orgDigital Electronics Module 5Bi-Stable Logic DevicesBi-stable devices (popularly called Flip-flops) described in Modules 5.2 to5.4, are sub-circuits, usually contained within ICs, and are the most basictype of 1-bit memory. They have outputs that can take up one of two stablestates, Logic 1 or logic 0 or off. Once the device is triggered into one ofthese two states by an external input pulse, the output remains in that stateuntil another pulse is used to reverse that state, so that a logic 1 outputbecomes logic 0 or vice versa. Again the circuit remains stable in this stateuntil an input signal is used to reverse the output state. Hence the circuit issaid to have Bi (two) stable output states.CountersVarious types of digital counters are described in Module 5.6.Consisting of arrangements of bi-stables, they are very widelyused in many types of digital systems from computer arithmeticto TV screens and digital clocks.Shift RegistersAlso consisting of arrays of bi-stable elements,the shift registers described in Module 5.7 aretemporary storage devices (memories) for multibit digital data. The data can be stored in theregister either one bit at a time (serial input) oras one or more bytes at a time (parallel input).The register can then output the data in either serial or parallel form. Shift registers are vital toreceiving or transmitting data in digital communications systems. They can also be used in digitalarithmetic for operations such as multiplication and division.A Simple ALUA simple arithmetic and logic unit (ALU) is described in Module 5.8 andcombines many of the combinational and sequential logic circuitsdescribed in modules 4 and 5 to demonstrate how a very complexapplication is built by combining a number of much simpler digital subcircuits.DIGITAL ELECTRONICS MODULE 05.PDF2 E. COATES 2007-2014

www.learnabout-electronics.orgDigital Electronics Module 55.1 Clock CircuitsWhat you’ll learn in Module 5.1After studying this section, you shouldbe able to:Understand the need for clock generators.Recognise clock generator circuits RC clocks Crystal controlled clocks.Understand the operation of commonclock generators.Clocks and TimingSignalsMost sequential logiccircuits are driven by aclock oscillator. Thisusually consists of anastable circuit producingregularpulsesthatshould ideally:1. Be constant in frequency.Many clock oscillators use a crystal to control the frequency. Because crystal oscillatorsgenerate normally high frequencies, where lower frequencies are required the original oscillatorfrequency is divided down from a very high frequency to a lower one using counter circuits.2. Have fast rising and falling edges to its pulses.It is the edges of the pulses that are important in timing the operation of many sequentialcircuits, the rise and fall times are usually be less than 100ns. The outputs of clock circuits willtypically have to drive more gates than any other output in a given system. To prevent this loaddistorting the clock signal, it is usual for clock oscillator outputs to be fed via a buffer amplifier.3. Have the correct logic levels.The signals produced by the clock circuits must have appropriate the logic levels for thecircuits being supplied.Some examples of clock oscillator circuits are given below.Simple Clock OscillatorFig 5.1.1 is probably the simplest oscillator possible, having onlythree components. Notice that the gate is a Schmitt inverter. Thisdevice has an extremely fast change over between logic states. Alsothe level at which it responds to an input change from 0 to 1 (Vt )is higher than the level at which it changes from 1 to 0 (Vt-). Theoperation of the circuit is as follows.Suppose the gate input is at logic 0, because the gate is an inverter,the output must be at logic 1, and C will therefore charge up via Rfrom the output. This will happen with the normal CR chargingcurve. Once Vt is reached at the gate input, the gate output willrapidly switch to 0. The resistor is now connected effectivelybetween the positive plate of C and zero volts. Thus the capacitornow discharges via R until the gate input voltage reduces to Vtwhen the output will change to logic 1 once more, starting thecharging and discharging cycle over again.Fig. 5.1.1 Basic SchmittTrigger OscillatorThis Schmitt RC oscillator can produce a pulse waveform with anexcellent wave shape and very fast rise and fall times. The mark tospace ratio, as shown in Fig 5.1.2 is approximately 1:3.Fig. 5.1.2 Typical BasicSchmitt Oscillator OutputDIGITAL ELECTRONICS MODULE 05.PDF3 E. COATES 2007-2014

www.learnabout-electronics.orgDigital Electronics Module 5The frequency of oscillation depends on the time constant of R and C, but is also affected by thecharacteristics of the logic family used. For the 74HC14 the frequency ( f )is calculated by:f 10.8RCWhen using the 74HCT14 the 0.8 correction factor is replacedby 0.67, however either of these formulae will give anapproximate frequency. Whichever logic family is used, thefrequency will vary with changes in supply voltage. Althoughthis basic oscillator gives an excellent performance in manysimple applications, if a stable frequency is an important factorin the choice of clock oscillator, there are of course betteroptions.Crystal Controlled Clock OscillatorFig. 5.1.3 uses three gates from a 74HCT04 IC, and a crystal toprovide an accurate frequency of oscillation. Here, the oscillatoris running at 3.276MHz but this can be reduced by dividing theoutput frequency down to a lower value by dividing it by 2 anumber of times using a series of flip-flops.Fig. 5.1.3 Crystal ControlledClock OscillatorThe top waveform in Fig 5.1.4 shows the clock signal generatedby Fig 5.1.3, and beneath it is the clock signal frequency dividedby 4 after passing it through two flip-flops. Notice that afterpassing the signal through flip-flops, as well as being reduced infrequency, the wave shape is considerably squarer and now has a1:1 mark to space ratio.Fig. 5.1.4 Clock FrequencyDivided by 4The 555 Timer as a Clock GeneratorAnother option in circuits not requiring very high frequency clock signals is to use the 555 Timer inastable mode as a clock generator. This IC is able to produce good quality pulse or square wavesignals over a wide range of frequencies, lower than those possible with crystal oscillators, also thefrequency stability will not be as good as with crystal controlled oscillators.Several oscillator design options are discussed in Oscillators Module 4.4Two Phase Clock SignalsSome older microprocessor systems required two-phase clock signals which, provided that thesource clock signal operated at twice the frequency required by the microprocessor, savedprocessing time as the microprocessor was able to perform two actions per clock cycle instead ofone.Producing a Two-Phase Clock SignalIf a clock signal with a 1:1 mark space ratio is used, twonon-overlapping clock pulses can be created, as shownin Fig. 5.1.5. These signals are usually called 01 and02 ( , the Greek letter phi is used to indicate phase).In Fig 5.1.5 a single clock signal having a 1:1 mark tospace ratio is fed into a JK flip-flop working in togglemode. This is achieved by making both J and K logic 1.DIGITAL ELECTRONICS MODULE 05.PDF4Fig. 5.1.5 Two-Phase Clock Circuit E. COATES 2007-2014

www.learnabout-electronics.orgDigital Electronics Module 5The active low PR and CLR inputs take no part in the operationof this circuit so are also tied to logic 1. In toggle mode the Q outputof the JK flip-flop inverts the logic levels at Q and Q at every fallingedge of the clock (CK) input, also Q and Q always remain atopposite logic states.Fig. 5.1.6 illustrates the operation of Fig 5.1.5. Each of the NANDgates will produce a logic 0 output whenever both its inputs are atlogic 1. The NAND gate producing 01 therefore creates a logic 0pulse whenever CK and Q are at logic 1, and the NAND gateproducing 02 creates a logic 0 pulse whenever CK and Q are atFig. 5.1.6 Producing NonOverlapping Clock Pulseslogic 1. Typical output waveforms are illustrated in Fig. 5.1.7.If positive going clock pulses are required, the outputs from theNAND gates may be inverted using Schmitt inverters, whichwill also help to sharpen the rise and fall times of the clockwaveforms.Distributing Clock SignalsFor more demanding applications there are very manyspecialised clock oscillator ICs available that are typicallyoptimised for a particular range of applications, such ascomputer hardware, wireless communications, automotive ormedical applications etc.Fig. 5.1.7 Two Phase ClockWaveformsClock Fan-outWhatever circuit is used to generate a clock signal, it is important that its output has sufficient fanout capability to drive the necessary number of ICs requiring a clock input, and that the clock signalis not degraded in amplitude, speed of its rise and fall times or accuracy of its frequency. Also, bymaintaining fast rise and fall times, ringing on the waveform can become a problem. The waveformshould be kept as close as possible to a perfect square wave shape.Circuit CapacitanceBecause the clock must feed many gates, the small capacitance of each of these gates will add, tobecome an appreciable capacitance, which loads the clock output tending to slow the rise and falltime of the clock signal. To avoid this, the clock output must have a low enough impedance torapidly charge and discharge any natural capacitance in the circuit. The usual way to achieve this isto feed the clock signal via a special clock buffer gate, which will have the necessary low outputimpedance and a large fan out factor. Schmitt trigger gates may also be used to restore the shapeand integrity of clock signals before they are applied to gates in different parts of the circuit.Cross-talkWhere the clock signal has to be distributed around large circuits, there is a greater chance ofintroducing noise, and possible ‘cross-talk’ where data in one conductor is radiated into anothernearby conductor. Problems such as this will increase the likelihood of ‘skew’ errors, i.e. clocksignals arriving at different parts of the circuit at slightly different times, due to small changes in thephase of some of the distributed clock signals. Miniaturisation brought about by surface mounttechnology can help minimise these problems. Also when clock signals need to be sent from onesystem to another over an external wired or wireless link it is common to use one of the severalECL or LVDS logic families with their differential outputs to minimise interference, and there aremany application specific ICs (ASICS) using these technologies for high frequency clockdistribution.DIGITAL ELECTRONICS MODULE 05.PDF5 E. COATES 2007-2014

www.learnabout-electronics.orgDigital Electronics Module 55.2 SR Flip-flopsWhat you’ll learn in Module 5.2After studying this section, you shouldbe able to:Describe SR flip-flop circuits and can: Describe typical applicationsfor SR flip-flops. Recognize standard circuitsymbols for SR flip-flops. Recognize SR flip-flopintegrated circuits.Recognise alternative forms of SR flipflops. Clocked SR flip-flop. High Activated SR flip-flops(The RS Latch). Compile truth tables for SRflip-flops. Construct timing diagrams toexplain the operation of SRflip-flops.Use circuit simulation software toconstruct SR flip-flops.Typical applications for SR Flip-flops.The basic building bock that makes computer memoriespossible, and is also used in many sequential logic circuitsis the flip-flop or bi-stable circuit. Just two inter-connectedlogic gates make up the basic form of this circuit whoseoutput has two stable output states. When the circuit istriggered into either one of these states by a suitable inputpulse, it